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ds001101-z8x0400 1 d ata s heet z8e001 1 f eature -r ich z8p lus o ne -t ime p rogrammable (otp) m icrocontroller features microcontroller core features all instructions execute in one 1 m s instruction cycle with a 10 mhz crystal 1k x 8 on-chip otp eprom memory 64 x 8 general-purpose registers (sram) six vectored interrupts with fixed priority operating speed: dce10 mhz six addressing modes: r, ir, x, d, ra, & im peripheral features 13 total input/output pins one 8-bit i/o port (port a) e i/o bit programmable e each bit programmable as push-pull or open- drain one 5-bit i/o port (port b) e i/o bit programmable e includes special functionality: stop-mode re- covery input, comparator inputs, selectable edge interrupts, and timer output one analog comparator 16-bit programmable watch-dog timer (wdt) software programmable timers configurable as: e two 8-bit standard timers and one 16-bit stan- dard timer, or e one 16-bit standard timer and one 16-bit pulse width modulator (pwm) timer additional features on-chip oscillator that accepts an xtal, ceramic res- onator, lc, or external clock programmable options: e eprom protect power reduction modes: e halt mode with peripheral units active e stop mode with all functionality shut down cmos/technology features low-power consumption 3.5v to 5.5v operating range @ 0 c to +70 c 4.5v to 5.5v operating range @ e40 c to +105 c 18-pin dip, soic, and 20-pin ssop packages. general description allowing easy software development, debug, and prototyp- ing, zilog?s new z8e001 microcontroller (mcu) offers a cost-effective one-time programmable (otp) solution to its single-chip z8plus mcu family. for applications demanding powerful i/o capabilities, the z8e001?s dedicated input and output lines are grouped into two ports, and are configurable under software control. both 8-bit and 16-bit on-chip timers, with a large number of user-selectable modes, offload the system of administer- part number rom (kb) ram* (bytes) speed (mhz) z8e001 1 64 10 note: * general-purpose
z8e001 z8plus otp microcontroller zilog 2 p r e l i m i n a r y ds001101-z8x0400 general description (continued) ing real-time tasks such as counting/timing and i/o data communications. note: all signals with an overline, , are active low. for example, b/ w (word is active low, only); b /w (byte is active low, only). power connections follow conventional descriptions be- low: connection circuit device power v cc v dd ground gnd v ss figure 1. functional block diagram one 16-bit std. timer interrupt control one analog comparator alu flag register pointer ram register machine timing otp prg. mem- program counter v cc gnd xtal port a port b i/o two 8-bit timers or one 16-bit pwm timer i/o re s et
z8e001 zilog z8plus otp microcontroller ds001101-z8x0400 p r e l i m i n a r y 3 figure 2. eprom programming mode block diagram z8e001 port a data mux eprom rom prot z8e001 mcu address generator pgm + test mode logic address mux d7e0 d7e0 ad9e0 ad9e0 ad9e0 d7e0 adclr/v pp pgm adclk xtal1 option bit
z8e001 z8plus otp microcontroller zilog 4 p r e l i m i n a r y ds001101-z8x0400 pin description figure 3. 18-pin dip/soic pin identification/eprom programming mode eprom programming mode pin # symbol function direction 1 pgm prog mode input 2e4 gnd ground 5 adclr/v pp clear clk./prog volt. input 6-9 d7ed4 data 7,6,5,4 input/output 10e13 d3ed0 data 3,2,1,0 input/output 14 v dd power supply 15 gnd ground 16 nc no connection 17 xtal1 1mhz clock input 18 adclk address clock input pgm gnd gnd gnd adclr/v pp d7 d6 d5 d4 adclk xtal1 nc gnd v dd d0 d1 d2 d3 18 18-pin dip 1 910
z8e001 zilog z8plus otp microcontroller ds001101-z8x0400 p r e l i m i n a r y 5 figure 4. 18-pin dip/soic pin identification standard mode pin # symbol function direction 1e4 pb1epb4 port b, pins 1,2,3,4 input/output 5 reset reset input 6-9 pa7epa4 port a, pins 7,6,5,4 input/output 10e13 pa3epa0 port a, pins 3,2,1,0 input/output 14 v cc power supply 15 v ss ground 16 xtal2 crystal osc. clock output 17 xtal1 crystal osc. clock input 18 pb0 port b, pin 0 input/output pb1 pb2 pb3 pb4 rst pa7 pa6 pa5 pa4 pbo xtal1 xtal2 v ss v cc pa0 pa1 pa2 pa3 18 dip 18-pin 1 910
z8e001 z8plus otp microcontroller zilog 6 p r e l i m i n a r y ds001101-z8x0400 pin description (continued) figure 5. 20-pin ssop pin identification standard mode pin # symbol function direction 1e4 pb1epb4 port b, pins 1,2,3,4 input/output 5 reset reset input 6 nc no connection 7e10 pa7epa4 port a, pins 7,6,5,4 input/output 11e14 pa3epa0 port a, pins 3,2,1,0 input/output 15 nc no connection 16 v cc power supply 17 v ss ground 18 xtal2 crystal osc. clock output 19 xtal1 crystal osc. clock input 20 pb0 port b, pin 0 input/output pb1 pb2 pb3 pb4 reset nc pa7 pa6 pa5 pa4 pbo xtal1 xtal2 v ss v cc nc pa0 pa1 pa2 pa3 20 ssop 20-pin 1 10 11
z8e001 zilog z8plus otp microcontroller ds001101-z8x0400 p r e l i m i n a r y 7 figure 6. 20-pin ssop pin identification/eprom programming mode eprom programming mode pin # symbol function direction 1 pgm prog mode input 2e4 gnd ground 5 adclr/v pp clear clk./prog volt. input 6 nc no connection 7e10 d7ed4 data 7,6,5,4 input/output 11e14 d3ed0 data 3,2,1,0 input/output 15 nc no connection 16 v dd power supply 17 gnd ground 18 nc no connection 19 xtal1 1mhz clock input 20 adclk address clock input pgm gnd gnd gnd adclr/v pp nc d7 d6 d5 d4 adclk xtal1 nc gnd v dd nc d0 d1 d2 d3 20 ssop 20-pin 1 10 11
z8e001 z8plus otp microcontroller zilog 8 p r e l i m i n a r y ds001101-z8x0400 absolute maximum ratings stresses greater than those listed under absolute maximum ratings can cause permanent damage to the device. this rat- ing is a stress rating only. functional operation of the device at any condition above those indicated in the operational sections of these specifications is not implied. exposure to absolute maximum rating conditions for an extended period can affect device reliability. total power dissipation should not exceed 880 mw for the package. power dissipation is calculated as follows: parameter min max units note ambient temperature under bias e40 +105 c storage temperature e65 +150 c voltage on any pin with respect to v ss e0.6 +7 v 1 voltage on v dd pin with respect to v ss e0.3 +7 v voltage on reset pin with respect to v ss e0.6 v dd +1 v 2 total power dissipation 880 mw maximum allowable current out of v ss 80 ma maximum allowable current into v dd 80 ma maximum allowable current into an input pin e600 +600 ma 3 maximum allowable current into an open-drain pin e600 +600 ma 4 maximum allowable output current sunk by any i/o pin 25 ma maximum allowable output current sourced by any i/o pin 25 ma maximum allowable output current sunk by port a 40 ma maximum allowable output current sourced by port a 40 ma maximum allowable output current sunk by port b 40 ma maximum allowable output current sourced by port b 40 ma notes: 1. applies to all pins except the reset pin and where otherwise noted. 2. there is no input protection diode from pin to v dd . 3. excludes xtal pins. 4. device pin is not at an output low state. total power dissipation = v dd x [i dd e (sum of i oh )] + sum of [(v dd e v oh ) x i oh ] + sum of (v 0l x i 0l )
z8e001 zilog z8plus otp microcontroller ds001101-z8x0400 p r e l i m i n a r y 9 standard test conditions the characteristics listed below apply for standard test con- ditions as noted. all voltages are referenced to ground. pos- itive current flows into the referenced pin (figure 7). capacitance t a = 25?c, v cc = gnd = 0v, f = 1.0 mhz, unmeasured pins returned to gnd. figure 7. test load diagram from output under test 150 pf parameter min max input capacitance 0 12 pf output capacitance 0 12 pf i/o capacitance 0 12 pf
z8e001 z8plus otp microcontroller zilog 10 p r e l i m i n a r y ds001101-z8x0400 dc electrical characteristics table 1. dc electrical characteristics pf t a = 0?c to +70?c standard temperatures typical 2 @ 25?c sym parameter v cc 1 min max units conditions notes v ch clock input high voltage 3.5v 0.7v cc v cc +0.3 1.3 v driven by external clock generator 5.5v 0.7v cc v cc +0.3 2.5 v driven by external clock generator v cl clock input low voltage 3.5v v ss e0.3 0.2v cc 0.7 v driven by external clock generator 5.5v v ss e0.3 0.2v cc 1.5 v driven by external clock generator v ih input high voltage 3.5v 5.5v 0.7v cc 0.7v cc v cc +0.3 v cc +0.3 1.3 2.5 v v v il input low voltage 3.5v 5.5v v ss e0.3 v ss e0.3 0.2v cc 0.2v cc 0.7 1.5 v v v oh output high voltage 3.5v v cc e0.4 3.1 v i oh = e2.0 ma 5.5v v cc e0.4 4.8 v i oh = e2.0 ma v ol1 output low voltage 3.5v 0.6 0.2 v i ol = +4.0 ma 5.5v 0.4 0.1 v i ol = +4.0 ma v ol2 output low voltage 3.5v 1.2 0.5 v i ol = +6 ma 5.5v 1.2 0.5 v i ol = +12 ma v rh reset input high voltage 3.5v 0.5v cc v cc 1.1 v 5.5v 0.5v cc v cc 2.2 v v rl reset input low voltage 3.5v v ss e0.3 0.2v cc 0.9 v 5.5v v ss e0.3 0.2v cc 1.4 v v offset comparator input offset voltage 3.5v 25.0 10.0 mv 5.5v 25.0 10.0 mv i il input leakage 3.5v e1.0 2.0 0.064 ma v in = 0v, v cc 5.5v e1.0 2.0 0.064 ma v in = 0v, v cc i ol output leakage 3.5v e1.0 2.0 0.114 a v in = 0v, v cc 5.5v e1.0 2.0 0.114 a v in = 0v, v cc v icr comparator input common mode voltage range 3.5v v ss e0.3 v cc e1.0 v 3 5.5v v ss e0.3 v cc e1.0 v 3 i ir reset input current 3.5v e10 e60 e30 a 5.5v e20 e180 e100 a
z8e001 zilog z8plus otp microcontroller ds001101-z8x0400 p r e l i m i n a r y 11 i cc supply current 3.5v 2.5 2.0 ma @ 10 mhz 4,5 5.5v 6.0 3.5 ma @ 10 mhz 4,5 i cc1 standby current 3.5v 2.0 1.0 ma halt mode v in = 0v, v cc @ 10 mhz 4,5 5.5v 4.0 2.5 ma halt mode v in = 0v, v cc @ 10 mhz 4,5 i cc2 standby current 3.5v 500 150 na stop mode v in = 0v, v cc 6 notes: 1. the v cc voltage specification of 3.5v guarantees 3.5v and the v cc voltage specification of 5.5 v guarantees 5.0 v 0.5 v. 2. typical values are measured at v cc = 3.3v and v cc = 5.0v; v ss = 0v = gnd. 3. for analog comparator input when analog comparator is enabled. 4. all outputs unloaded and all inputs are at v cc or v ss level. 5. cl1 = cl2 = 22 pf. 6. same as note 4 except inputs at v cc . table 1. dc electrical characteristics (continued) pf t a = 0?c to +70?c standard temperatures typical 2 @ 25?c sym parameter v cc 1 min max units conditions notes
z8e001 z8plus otp microcontroller zilog 12 p r e l i m i n a r y ds001101-z8x0400 dc electrical characteristics (continued) table 2. dc electrical characteristics t a = e40?c to +105?c extended temperatures typical 2 @ 25?c sym parameter v cc 1 min max units conditions notes v ch clock input high voltage 4.5v 0.7 v cc v cc +0.3 2.5 v driven by external clock generator 5.5v 0.7 v cc v cc +0.3 2.5 v driven by external clock generator v cl clock input low voltage 4.5v v ss e0.3 0.2 v cc 1.5 v driven by external clock generator 5.5v v ss e0.3 0.2 v cc 1.5 v driven by external clock generator v ih input high voltage 4.5v 0.7 v cc v cc +0.3 2.5 v 5.5v 0.7 v cc v cc +0.3 2.5 v v il input low voltage 4.5v v ss e0.3 0.2 v cc 1.5 v 5.5v v ss e0.3 0.2 v cc 1.5 v v oh output high voltage 4.5v v cc e0.4 4.8 v i oh = e2.0 ma 5.5v v cc e0.4 4.8 v i oh = e2.0 ma v ol1 output low voltage 4.5v 0.4 0.1 v i ol = +4.0 ma 5.5v 0.4 0.1 v i ol = +4.0 ma v ol2 output low voltage 4.5v 1.2 0.5 v i ol = +12 ma 5.5v 1.2 0.5 v i ol = +12 ma v rh reset input high voltage 4.5v 0.5v cc v cc 1.1 v 5.5v 0.5v cc v cc 2.2 v v offset comparator input offset voltage 4.5v 25.0 10.0 mv 5.5v 25.0 10.0 mv i il input leakage 4.5v e1.0 2.0 <1.0 a v in = 0v, v cc 5.5v e1.0 2.0 <1.0 a v in = 0v, v cc i ol output leakage 4.5v e1.0 2.0 <1.0 a v in = 0v, v cc 5.5v e1.0 2.0 <1.0 a v in = 0v, v cc v icr comparator input common mode voltage range 4.5v 0 v cc e1.5v v 3 5.5v 0 v cc e1.5v v 3 i ir reset input current 4.5v e18 e180 e112 ma 5.5v e18 e180 e112 ma
z8e001 zilog z8plus otp microcontroller ds001101-z8x0400 p r e l i m i n a r y 13 i cc supply current 4.5v 7.0 4.0 ma @ 10 mhz 4,5 5.5v 7.0 4.0 ma @ 10 mhz 4,5 i cc1 standby current 4.5v 2.0 1.0 ma halt mode v in = 0v, v cc @ 10 mhz 4,5 5.5v 2.0 1.0 ma halt mode v in = 0v, v cc @ 10 mhz 4,5 i cc2 standby current 4.5v 700 250 na stop mode v in = 0v,v cc 6 5.5v 700 250 na stop mode v in = 0v,v cc 6 notes: 1. the v cc voltage specification of 4.5v and 5.5v guarantees 5.0v 0.5v. 2. typical values are measured at v cc = 3.3v and v cc = 5.0v; v ss = 0v = gnd. 3. for analog comparator input when analog comparator is enabled. 4. all outputs unloaded and all inputs are at v cc or v ss level. 5. cl1 = cl2 = 22 pf. 6. same as note 4 except inputs at v cc . table 2. dc electrical characteristics (continued) t a = e40?c to +105?c extended temperatures typical 2 @ 25?c sym parameter v cc 1 min max units conditions notes
z8e001 z8plus otp microcontroller zilog 14 p r e l i m i n a r y ds001101-z8x0400 ac electrical characteristics figure 8. ac electrical timing diagram table 3. additional timing t a = 0?c to +70?c t a = e40?c to +105?c @ 10 mhz no symbol parameter v cc 1 min max units notes 1 tpc input clock period 3.5v 100 dc ns 2 5.5v 100 dc ns 2 2 trc,tfc clock input rise and fall times 3.5v 15 ns 2 5.5v 15 ns 2 3 twc input clock width 3.5v 50 ns 2 5.5v 50 ns 2 4 twil int. request input low time 3.5v 70 ns 2 5.5v 70 ns 2 5 twih int. request input high time 3.5v 5tpc 2 5.5v 5tpc 2 6 twsm stop mode recovery width spec. 3.5v 12 ns 5.5v 12 ns 7 tost oscillator start-up time 3.5v 5tpc 5.5v 5tpc notes: 1. the v dd voltage specification of 3.5v guarantees 3.5v. the v dd voltage specification of 5.5v guarantees 5.0v 0.5v. 2. timing reference uses 0.7 v cc for a logic 1 and 0.2 v cc for a logic 0. 13 3 2 2 clock irq n 4 5
z8e001 zilog z8plus otp microcontroller ds001101-z8x0400 p r e l i m i n a r y 15 z8plus core the z8e001 is based on the zilog z8plus core architec- ture. this core is capable of addressing up to 64kbytes of program memory and 4kbytes of ram. register ram is accessed as either 8 or 16 bit registers using a combination of 4, 8, and 12 bit addressing modes. the architecture sup- ports up to 15 vectored interrupts from external and internal sources. the processor decodes 44 cisc instructions using six addressing modes. see the z8plus user?s manual for more information. reset this section describes the z8e001 reset conditions, reset timing, and register initialization procedures. reset is gen- erated by the reset pin, watch-dog timer (wdt), and stop-mode recovery (smr). a system reset overrides all other operating conditions and puts the z8e001 into a known state. to initialize the chip?s internal logic, the reset input must be held low for at least 30 xtal clock cycles. the control registers and ports are reset to their default conditions after a reset from the reset pin. the control registers and ports are not reset to their default conditions after wakeup from stop mode or wdt timeout. during reset , the program counter is loaded with 0020h. i/o ports and control registers are configured to their default reset state. resetting the z8e001 does not affect the con- tents of the general-purpose registers. reset pin operation the z8e001 hardware reset pin initializes the control and peripheral registers, as shown in table 4. specific reset values are shown by 1 or 0, while bits whose states are un- changed or unknown from power-up are indicated by the letter u. reset must be held low until the oscillator stabilizes, for an additional 30 xtal clock cycles, in order to be sure that the internal reset is complete. the reset pin has a schmitt- trigger input with a trip point. there is no high side pro- tection diode. the user should place an external diode from reset to v cc . a pull-up resistor on the reset pin is ap- proximately 500 k w , typical. program execution starts 10 xtal clock cycles after re- set has returned high. the initial instruction fetch is from location 0020h. figure 9 indicates reset timing. after a reset, the first routine executed must be one that ini- tializes the tctlhi control register to the required system configuration, followed by initialization of the remaining control registers. table 4. control and peripheral registers register (hex) register name bits comments 76543210 ff stack pointer 0 0 uuuuuu stack pointer is not affected by reset fe reserved fd register pointer uuuu 0000 register pointer is not affected by reset fc flags uuuuuu * * only wdt & smr flags are affected by reset fb interrupt mask 00000000 all interrupts masked by reset fa interrupt request 00000000 all interrupt requests cleared by reset f9ef0 reserved efee0 virtual copy virtual copy of the current working register set dfed8 reserved
z8e001 z8plus otp microcontroller zilog 16 p r e l i m i n a r y ds001101-z8x0400 reset pin operation (continued) d7 port b special function 00000000 deactivates all port special functions after reset d6 port b directional control 00000000 defines all bits as inputs in portb after reset d5 port b output uuuuuuuu output register not affected by reset d4 port b input uuuuuuuu current sample of the input pin following reset d3 port a special function 00000000 deactivates all port special functions after reset d2 port a directional control 00000000 defines all bits as inputs in porta after reset d1 port a output uuuuuuuu output register not affected by reset d0 port a input uuuuuuuu current sample of the input pin following reset cf reserved ce reserved cd t1val uuuuuuuu cc t0val uuuuuuuu cb t3val uuuuuuuu ca t2val uuuuuuuu c9 t3ar uuuuuuuu c8 t2ar uuuuuuuu c7 t1arhi uuuuuuuu c6 t0arhi uuuuuuuu c5 t1arlo uuuuuuuu c4 t0arlo uuuuuuuu c3 wdthi 11111111 c2 wdtlo 11111111 c1 tctlhi 11111000wdt enabled in halt mode, wdt timeout at maximum value, stop mode disabled c0 tctllo 00000000 all standard timers are disabled note: *the smr and wdt flags are set indicating the source of the reset . table 4. control and peripheral registers (continued) register (hex) register name bits comments 76543210
z8e001 zilog z8plus otp microcontroller ds001101-z8x0400 p r e l i m i n a r y 17 table 5. flag register bit d1, d0 d1 d0 reset source 0 0 reset pin 0 1 smr recovery 1 0 wdt reset 1 1 reserved figure 9. reset timing figure 10. example of external power-on reset (por) circuit first machine cycle clock reset first instruction fetch hold low for 30 xtal periods (minimum) 10 xtal clock cycles 1 f 100 k? reset 1k? v cc z8e001 v cc 500 k?
z8e001 z8plus otp microcontroller zilog 18 p r e l i m i n a r y ds001101-z8x0400 reset pin operation (continued) figure 11. z8e001 reset circuitry with wdt and smr xtal /64 tctlhi d6,d5,d4 3 smr recovery smr (pb0) wdtrst 16-bit timer wdt tap select wdtrst watchdog timer smr logic
z8e001 zilog z8plus otp microcontroller ds001101-z8x0400 p r e l i m i n a r y 19 z8e001 watch-dog timer (wdt) the wdt is a retriggerable one-shot 16-bit timer that resets the z8e001 if it reaches its terminal count. the wdt is driv- en by the xtal2 clock pin. to provide the longer timeout periods required in applications, the watchdog timer is only updated every 64th clock cycle. when operating in the run or halt modes, a wdt timeout reset is functionally equivalent to an interrupt vectoring the pc to 0020h and setting the wdt flag to a one state. coming out of reset , the wdt is fully enabled with its timeout value set at the maximum value, unless otherwise programmed during the first instruction. subsequent executions of the wdt in- struction, reinitialize the watchdog timer registers (c2h and c3h), to their initial values as defined by bits d6, d5, and d4 of the tctlhi register. the wdt cannot be disabled except on the first cycle after reset , and if the device en- ters stop mode. the wdt instruction should be executed often enough to provide some margin before allowing the wdt registers to get near 0. because the wdt timeout periods are relatively long, a wdt reset will occur in the unlikely event that the wdt times out on exactly the same cycle that the wdt in- struction is executed. the wdt and smr flags are the only flags that are affected by the external reset pin. reset clears both the wdt and smr flags. a wdt timeout sets the wdt flag. the stop instruction sets the smr flag. this behavior enables software to determine whether a pin reset occurred, or whether a wdt timeout occurred, or whether a return from stop mode occurred. reading the wdt and smr flags does not reset it to zero, the user must clear it via software. note: failure to clear the smr flag can result in undefined be- havior. figure 12. z8e001 tctlhi register for control of wdt d7 d6 d5 d4 d3 d2 d1 d0 0c1 tctlhi reserved (must be 0) 0 = stop mode enabled 1 = stop mode disabled* d6 d5 d4 wdt timeout value ---- ---- ---- -------------------------------- 0 0 0 disabled 0 0 1 65,536 tpc 0 1 0 131,072 tpc 0 1 1 262,144 tpc 1 0 0 524,288 tpc 1 0 1 1,048,576 tpc 1 1 0 2,097,152 tpc 1 1 1 4,194,304 tpc* (xtal clocks to timeout) 1 = wdt enabled in halt mode* 0 = wdt disabled in halt mode *designates default value after reset
z8e001 z8plus otp microcontroller zilog 20 p r e l i m i n a r y ds001101-z8x0400 note: the wdt can only be disabled via software if the first instruction out of reset performs this function. logic within the z8e001 detects that it is in the process of ex- ecuting the first instruction after the part leaves reset . during the execution of this instruction, the upper five bits of the tctlhi register can be written. after this first instruction, hardware does not allow the upper five bits of this register to be written. the tctlhi bits for control of the wdt are described be- low: wdt time select (d6, d5, d4). bits 6, 5, and 4 determine the time-out period. table 6 indicates the range of timeout values that can be obtained. the default values of d6, d5, and d4 are all 1, thus setting the wdt to its maximum tim- eout period when coming out of reset . wdt during halt (d7). this bit determines whether or not the wdt is active during halt mode. a 1 indicates active during halt. a 0 prevents the wdt from resetting the part while halted.coming out of reset, the wdt is en- abled during halt mode. stop mode (d3). coming out of reset , the z8e001 stop mode is disabled. if an application requires use of stop mode, bit d3 must be cleared immediately upon leaving reset . if bit d3 is set, the stop instruction exe- cutes as a nop. if bit d3 is cleared, the stop instruction enters stop mode. whenever the z8e001 wakes up after having been in stop mode, the stop mode is again dis- abled. bits 2, 1 and 0. these bits are reserved and must be 0. power-down modes i n addition to the standard run mode, the z8 e001 mcu sup- ports two power-down modes to minimize device current con- sumption. the two modes supported are halt and stop. halt mode operation the halt mode suspends instruction execution and turns off the internal cpu clock. the on-chip oscillator circuit remains active so the internal clock continues to run and is applied to the timers and interrupt logic. to enter the halt mode, the z8e001 only requires a halt instruction. it is not necessary to execute a nop instruction immediately before the halt instruction. the halt mode can be exited by servicing an interrupt (either externally or internally) generated. upon comple- tion of the interrupt service routine, the user program con- tinues from the instruction after the halt instruction. the halt mode can also be exited via a reset activation or a watch-dog timer (wdt) timeout. in these cases, pro- gram execution restarts at the reset restart address 0020h. table 6. wdt time-out d6 d5 d4 crystal clocks* to timeout time-out using a 10 mhz crystal 0 0 0 disabled disabled 0 0 1 65,536 tpc 6.55 ms 0 1 0 131,072 tpc 13.11 ms 0 1 1 262,144 tpc 26.21 ms 1 0 0 524,288 tpc 52.43 ms 1 0 1 1,048,576 tpc 104.86 ms 1 1 0 2,097,152 tpc 209.72 ms 1 1 1 4,194,304 tpc 419.43 ms note: * tpc=xtal clock cycle. the default on reset is d6=d5=d4=1. 7f halt ; enter halt mode
z8e001 zilog z8plus otp microcontroller ds001101-z8x0400 p r e l i m i n a r y 21 stop mode operation the stop mode provides the lowest possible device stand- by current. this instruction turns off the on-chip oscillator and internal system clock. to enter the stop mode, the z8e001 only requires a stop instruction. it is not necessary to execute a nop instruc- tion immediately before the stop instruction. the stop mode is exited by any one of the following re- sets: reset pin or a stop-mode recovery source. upon reset generation, the processor always restarts the applica- tion program at address 0020h, and the stop mode flag is set. reading the stop mode flag does not clear it. the user must clear the stop mode flag with software. note: failure to clear the stop mode flag can result in unde- fined behavior. the z8e001 provides a dedicated stop-mode recovery (smr) circuit. in this case, a low-level applied to input pin pb0 triggers an smr. to use this mode, pin pb0 (i/o port b, bit 0) must be configured as an input before the stop mode is entered. the low level on pb0 must be held for a minimum pulse width t wsm plus any oscillator startup time. program execution starts at address 20hex after pb0 is raised back to a high level. notes: use of the pb0 input for the stop mode recovery does not initialize the control registers. the stop mode current (i cc2 ) is minimized when: ? v cc is at the low end of the devices operating range. ? output current sourcing is minimized. ? all inputs (digital and analog) are at the low or high rail voltages. clock the z8e001 mcu derives its timing from on-board clock circuitry connected to pins xtal1 and xtal2. the clock circuitry consists of an oscillator, a glitch filter, a divide- by-two shaping circuit, a divide-by-four shaping circuit, and a divide-by-eight shaping circuit. figure 13 illustrates the clock circuitry. the oscillator?s input is xtal1 and its output is xtal2. the clock can be driven by a crystal, a ceramic resonator, lc clock, or an external clock source. 6f stop ;enter stop mode figure 13. z8e001 clock circuit ? 2 xtal2 xtal1 glitch filter ? 4 ? 8 wdt clock timer clock machine clock (5 cycles per in- struction)
z8e001 z8plus otp microcontroller zilog 22 p r e l i m i n a r y ds001101-z8x0400 oscillator operation the z8e001 mcu uses a pierce oscillator with an internal feedback resistor (figure 14). the advantages of this circuit are low-cost, large output signal, low-power level in the crystal, stability with respect to v cc and temperature, and low impedances (not disturbed by stray effects). one draw back is the requirement for high gain in the am- plifier to compensate for feedback path losses. the oscil- lator amplifies its own noise at start-up until it settles at the frequency that satisfies the gain/phase requirements (a x b = 1; where a = v o /v i is the gain of the amplifier and b = v i /v o is the gain of the feedback element). the total phase shift around the loop is forced to zero (360 degrees). v in must be in phase with itself; therefore, the amplifier/inverter provides a 180-degree phase shift, and the feedback element is forced to provide the other 180-degree phase shift. r1 is a resistive component placed from output to input of the amplifier. the purpose of this feedback is to bias the am- plifier in its linear region and provide the start-up transition. capacitor c 2 , combined with the amplifier output resis- tance, provides a small phase shift. it also provides some attenuation of overtones. capacitor c 1 , combined with the crystal resistance, pro- vides an additional phase shift. c 1 and c 2 can affect the start-up time if they increase dra- matically in size. as c 1 and c 2 increase, the start-up time increases until the oscillator reaches a point where it does not start up any more. it is recommended for fast and reliable oscillator start-up (over the manufacturing process range) that the load capac- itors be sized as low as possible without resulting in over- tone operation. layout traces connecting crystal, caps, and the z8e001 oscillator pins should be as short and wide as possible, to reduce par- asitic inductance and resistance. the components (caps, crystal, resistors) should be placed as close as possible to the oscillator pins of the z8e001. the traces from the oscillator pins of the ic and the ground side of the lead caps should be guarded from all other traces (clock, v cc , address/data lines, system ground) to reduce cross talk and noise injection. guarding is usually accom- plished by keeping other traces and system ground trace planes away from the oscillator circuit, and by placing a z8e001 device v ss ground ring around the traces/compo- nents. the ground side of the oscillator lead caps should be connected to a single trace to the z8e001 v ss (gnd) pin. it should not be shared with any other system ground trace or components except at the z8e001 device v ss pin. the objective is to prevent differential system ground noise in- jection into the oscillator (figure 15). indications of an unreliable design there are two major indicators that are used in working de- signs to determine their reliability over full lot and temper- ature variations. they are: start-up time. if start-up time is excessive, or varies wide- ly from unit to unit, there is probably a gain problem. to fix the problem, the capacitors c1/c2 require reduction. the amplifier gain is either not adequate at frequency, or the crystal rs are too large. output level. the signal at the amplifier output should swing from ground to v cc to indicate adequate gain in the amplifier. as the oscillator starts up, the signal amplitude grows until clipping occurs. at that point, the loop gain is effectively reduced to unity, and constant oscillation is achieved. a signal of less than 2.5 volts peak-to-peak is an indication that low gain can be a problem. either c 1 or c 2 should be made smaller, or a low-resistance crystal should be used. circuit board design rules the following circuit board design rules are suggested: to prevent induced noise, the crystal and load capacitors should be physically located as close to the z8e001 as possible. signal lines should not run parallel to the clock oscillator inputs. in particular, the crystal input circuitry and the in- ternal system clock output should be separated as much as possible. figure 14. pierce oscillator with internal feedback circuit xtal2 z8e001 v ss xtal1 c1 c2 r i v 1 a v 0
z8e001 zilog z8plus otp microcontroller ds001101-z8x0400 p r e l i m i n a r y 23 v cc power lines should be separated from the clock os- cillator input circuitry. resistivity between xtal1 or xtal2 (and the other pins) should be greater than 10 m w . crystals and resonators crystals and ceramic resonators (figure 16) should have the following characteristics to ensure proper oscillation: depending on the operation frequency, the oscillator can re- quire additional capacitors, c1 and c2, as shown in figure 16 and figure 17. the capacitance values are dependent on the manufacturer?s crystal specifications. figure 15. circuit board design rules xtal2 v ss xtal1 board design example v ss z8e001 z8e001 z8e001 c1 c2 clock generator circuit signals a b signal c (parallel traces must be avoided) (top view) 17 16 15 17 16 xtal1 xtal2 x1 x2 pb0 v cc crystal cut at (crystal only) mode parallel, fundamental mode crystal capacitance <7pf load capacitance 10pf < cl < 220 pf, 15 typical resistance 100 ohms max
z8e001 z8plus otp microcontroller zilog 24 p r e l i m i n a r y ds001101-z8x0400 oscillator operation (continued) in most cases, the r d is 0 ohms and r f is infinite. these specifications are determined and specified by the crys- tal/ceramic resonator manufacturer. the r d can be in- creased to decrease the amount of drive from the oscillator output to the crystal. it can also be used as an adjustment to avoid clipping of the oscillator signal to reduce noise. the r f can be used to improve the start-up of the crystal/ceramic resonator. the z8e001 oscillator already has an internal shunt resistor in parallel to the crystal/ceramic resonator. figure 16, figure 17, and figure 18 recommend that the load capacitor ground trace connect directly to the v ss (gnd) pin of the z8e001. this requirement assures that no system noise is injected into the z8e001 clock. this trace should not be shared with any other components except at the v ss pin of the z8e001. note: a parallel resonant crystal or resonator data sheet speci- fies a load capacitor value that is a series combination of c 1 and c 2 , including all parasitics (pcb and holder). figure 16. crystal/ceramic resonator oscillator figure 17. lc clock xtal2 z8e001 v ss xtal1 c1 c2 r f r d xtal2 z8e001 v ss xtal1 c1 c2 l figure 18. external clock xtal2 z8e001 v ss xtal1 n/c
z8e001 zilog z8plus otp microcontroller ds001101-z8x0400 p r e l i m i n a r y 25 lc oscillator the z8e001 oscillator can use a lc network to generate a xtal clock (figure 17). the frequency stays stable over v cc and temperature. the oscillation frequency is determined by the equation: where l is the total inductance including parasitics, and c t is the total series capacitance including parasitics. simple series capacitance is calculated using the equation at the top of the next column. a sample calculation of capacitance c 1 and c 2 for 5.83 mhz frequency and inductance value of 27 h is displayed as follows: timers for the z8e001, 8-bit timers (t0 and t1) are available to function as a pair of independent 8-bit standard timers, or they can be cascaded to function as a 16-bit pwm timer. in addition to t0 and t1, extra 8-bit timers (t2 and t3) are provided, but they can only operate in cascade to function as a 16-bit standard timer. frequency = 1 2 p ( lc t ) 1/2 1/ c t if c 1 1/c t c 1 = = = = 1/c 1 + 1/c 2 c 2 2 c 1 2c t 5.83 (10^6) = 1 2 1 [2.7 (10 -6 ) c t ] o c t = 27.6 pf thus c 1 = 55.2 pf and c 2 = 55.2 pf. figure 19. z8e001 16-bit standard timer enable tctll0 (d5) irq5 (t23) 16-bit down counter internal data bus t2val t3val osc/8 t3ar t2ar
z8e001 z8plus otp microcontroller zilog 26 p r e l i m i n a r y ds001101-z8x0400 timers (continued) figure 20. 8-bit standard timers figure 21. 16-bit standard pwm timer enable tctll0 (d2-d0) irq2 (t1) internal data bus osc/8 t1arhi t1arlo t1val 8-bit down counter (not used in this mode) 8-bit standard tim er enable tctll0 (d2-d0) irq2 (t0) internal data bus osc/8 t0arhi t0arlo t0val 8-bit down counter (not used in this mode) 8-bit standard tim er 16-bit down counter internal data bus high side pwm low side t1arhi t1arlo irq0 irq2 t1val t1 t0 internal data bus t0arhi osc/8 t0arlo t0val edge detect logic t out
z8e001 zilog z8plus otp microcontroller ds001101-z8x0400 p r e l i m i n a r y 27 each 8-bit timer is provided a pair of registers, which are both readable and writable. one of the registers is defined to contain the auto-initialization value for the timer, while the second register contains the current value for the timer. when a timer is enabled, the timer decrements whatever value is currently held in its count register, and then con- tinues decrementing until it reaches 0. at this time, an in- terrupt is generated and the contents of the auto-initializa- tion register optionally copy into the count value register. if auto-initialization is not enabled, the timer stops counting upon reaching 0, and control logic clears the appropriate control register bit to disable the timer. this operation is re- ferred to as single-shot. if auto-initialization is enabled, the timer continues counting from the initialization value. software should not attempt to use registers that are defined as having timer functionality. software is allowed to write to any register at any time, but care should be taken if timer registers are updated while the timer is enabled. if software updates the count value while the timer is in operation, the timer continues counting based upon the software-updated value. note: strange behavior can result if the software update oc- curred at exactly the point that the timer was reaching 0 to trigger an interrupt and/or reload. similarly, if software updates the initialization value reg- ister while the timer is active, the next time that the timer reaches 0, it initializes using the updated value. note: strange behavior could result if the initialization value register is being written while the timer is in the process of being initialized. whether initialization is done with the new or old value is a function of the exact timing of the write operation. in all cases, the z8e001 prioritizes the software write above that of a decrementer writeback; however, when hardware clears a control register bit for a timer that is configured for single-shot operation, the clearing of the control bit over- rides a software write. reading either register can be done figure 22. tctllo register d7 d6 d5 d4 d3 d2 d1 d0 0c0 tctllo timer status d2 d1 d0 t0 t1 t01 ---- ---- --- ------------ ------------ --------------- 0 0 0 disab. disab. 0 0 1 enab. disab. 0 1 0 disab. enab. 0 1 1 enab. enab. 1 0 0 enab.(*) 1 0 1 enab.(*) disab. 1 1 0 disab. enab.(*) 1 1 1 enab.(*) enab.(*) (note: (*) indicates auto-reload is active.) reserved (must be 0) 1 = t23 16-bit timer enabled with auto-reload active 0 = t2 and t3 timers disabled reserved (must be 0) note: timer t01 is a 16-bit pwm timer formed by cascading 8-bit timers t1 (msb) and t0 (lsb). t23 is a standard 16-bit timer formed by cascading 8-bit timers t3 (msb) and t2 (lsb).
z8e001 z8plus otp microcontroller zilog 28 p r e l i m i n a r y ds001101-z8x0400 timers (continued) at any time, and will have no effect on the functionality of the timer. if a timer pair is defined to operate as a single 16-bit entity, the entire 16-bit value must reach 0 before an interrupt is generated. in this case, a single interrupt is generated, and the interrupt corresponds to the even 8-bit timer. example: timers t2 and t3 are cascaded to form a single 16- bit timer, so the interrupt for the combined timer is defined to be that of timer t2 rather than t3. when a timer pair is specified to act as a single 16-bit timer, the even timer registers in the pair (timer t0 or t2) is defined to hold the timer?s least significant byte. in contrast, the odd timer in the pair holds the timer?s most significant byte. in parallel with the posting of the interrupt request, the in- terrupting timer?s count value is initialized by copying the contents of the auto-initialization value register to the count value register. it should be noted that any time that a timer pair is defined to act as a single 16-bit timer, that the auto- reload function is performed automatically. all 16-bit tim- ers continue counting while their interrupt requests are ac- tive, and each operates in a free-running manner. if interrupts are disabled for a long period of time, it is pos- sible for the timer to decrement to 0 again before its initial interrupt has been responded to. this condition is termed a degenerate case, and hardware is not required to detect it. when the timer control register is written, all timers that are enabled by the write begins counting using the value that is held in the count register. in this case, an auto-initializa- tion is not performed. all timers can receive an internal clock source only. each timer that is enabled is updated ev- ery 8th xtal clock cycle. if t0 and t1 are defined to work independently, then each works as an 8-bit timer with a single auto-initialization reg- ister (t0arlo for t0, and t1arlo for t1). each timer asserts its predefined interrupt when it times out, optionally performing the auto-initialization function. if t0 and t1 are cascaded to form a single 16-bit timer, then the single 16- bit timer is capable of performing as a pulse-width mod- ulator (pwm). this timer is referred to as t01 to distinguish it as having special functionality that is not available when t0 and t1 act independently. when t01 is enabled, it can use a pair of 16-bit auto-ini- tialization registers. in this mode, one 16-bit auto-initial- ization value is composed of the concatenation of t1arlo and t0arlo. the second auto-initialization value is com- posed of the concatenation of t1arhi and t0arhi. when t01 times out, it alternately initializes its count value using the lo auto-init pair, followed by the hi auto-init pair. this functionality corresponds to a pwm, where the t1 interrupt defines the end of the hi section of the waveform, and the t0 interrupt marks the end of the lo portion of the pwm waveform. to use the cascaded timers as a pwm, one must initialize the t0 and t1 count registers to work in conjunction with the port pin. the user should initialize the t0 and t1 count registers to the pwm_hi auto-init value to obtain the re- quired pwm behavior. the pwm is arbitrarily defined to use the lo autoreload registers first, implying that it had just timed out after beginning in the hi portion of the pwm waveform. as such, the pwm is defined to assert the t1 interrupt after the first timeout interval. after the auto-initialization has been completed, decre- menting occurs for the number of counts defined by the pwm_lo registers. when decrementing again reaches 0, the t0 interrupt is asserted; and auto-init using the pwm_hi registers occurs. decrementing occurs for the number of counts defined by the pwm_hi registers until reaching 0. from there, the t1 interrupt is asserted, and the cycle begins again. the internal timers can be used to trigger external events by toggling the pb1 output when generating an interrupt. this functionality can only be achieved in conjunction with the port unit defining the appropriate pin as an output signal with the timer output special function enabled. in this mode, the appropriate port output is toggled when the timer count reaches 0, and continues toggling each time that the timer times out. t out mode the portb special function register ptbsfr (0d7h) (fig- ure 23) is used in conjunction with the port b directional control register ptbdir (0d6) (figure 24) to configure pb1 for t out operation for timer0. in order for t out to function, pb1 must be defined as an output line by setting ptbdir bit 1 to 1. configured in this way, pb1 has the ca- pability of being a clock output for timer0, toggling the pb1 output pin on each timer0 timeout. at end-of-count, the interrupt request line irq0, clocks a toggle flip-flop. the output of this flip-flop drives the t out line, pb1. in all cases, when timer0 reaches its end-of-count, t out toggles to its opposite state (figure 25). if, for ex- ample, timer0 is in continuous counting mode, t out has a 50 percent duty cycle output. this duty cycle can easily be controlled by varying the initial values after each end- of-count.
z8e001 zilog z8plus otp microcontroller ds001101-z8x0400 p r e l i m i n a r y 29 figure 23. portb special function register (t out operation) figure 24. port b directional control register figure 25. timer t0 output through t out d7 d6 d5 d4 d3 d2 d1 d0 0d7 ptbsfr 1 = enable bit 0 as smr input 0 = no special functionality 1 = enable bit 1 as timer0 output 0 = no special functionality 1 = enable bit 2 as int1 input 0 = no special functionality d4 d3 compar. interrupts --- --- -------------- ------------------- 0 0 disabled disabled 0 1 enabled disabled 1 0 disabled enabled 1 1 enabled enabled bit 3: comp. ref. input bit 4: comp. signal input/ int0/int2 reserved (must be 0) d7 d6 d5 d4 d3 d2 d1 d0 0d6 ptbdir reserved (must be 0) 1 = bit n set as output 0 = bit n set as input t out pb1 irq0 (t0 end-of-count) ? 2
z8e001 z8plus otp microcontroller zilog 30 p r e l i m i n a r y ds001101-z8x0400 reset conditions after a hardware reset , the timers are disabled. see table 4 for timer control, value, and auto-initialization register status after reset . i/o ports the z8e001 has 13 lines dedicated to input and output. these lines are grouped into two ports known as port a and port b. port a is an 8-bit port, bit programmable as either inputs or outputs. port b can be programmed to provide standard input/output or the following special functions: timer0 output, comparator input, smr input, and external interrupt inputs. all ports have push-pull cmos outputs. in addition, the outputs of port a on a bit-wise basis can be configured for open-drain operation.the ports operate on a bit-wise basis. as such, the register values for/at a given bit position only affect the bit in question. each port is defined by a set of four control registers. see figure 27. directional control and special function registers each port on the z8e001 has a dedicated directional con- trol register that determines (on a bit-wise basis) whether a given port bit operates as either an input or an output. each port on the z8e001 has a special function register that, in conjunction with the directional control register, implements (on a bit-wise basis), any special functionality that can be defined for each particular port bit. input and output value registers each port has an output value register and a pf input val- ue register. for port bits configured as an input by means of the directional control register, the input value reg- ister for that bit position contains the current synchronized input value. for port bits configured as an output by means of the di- rectional control register, the value held in the correspond- ing bit of the output value register is driven directly onto the output pin. the opposite register bit for a given pin (the output register bit for an input pin and the input register bit for an output pin) holds their previous value. these bits are not changed and don?t have any effect on the hardware. read/write operations the control for each port is done on a bit-wise basis. all bits are capable of operating as inputs or outputs, depending upon the setting of the port?s directional control register. if configured as an input, each bit is provided a schmitt- trigger. the output of the schmitt-trigger is latched twice to perform a synchronization function, and the output of the synchronizer is fed to the port input register, which can be read by software. a write to a port input register has the effect of updating the contents of the input register, but subsequent reads do not necessarily return the same value that was written. if the bit in question is defined as an input, the input register for that bit position contains the current synchronized input val- ue. thus, writes to that bit position is overwritten on the next clock cycle with the newly sampled input data. however, if the particular port bit is programmed as an output, the in- put register for that bit retains the software-updated value. the port bits that are programmed as outputs do not sample the value being driven out. any bit in either port can be defined as an output by setting the appropriate bit in the directional control register. if such is the case, the value held in the appropriate bit of the port output register is driven directly onto the output pin. table 7. z8e001 i/o ports registers register address identifier port b special function od7h ptbsfr port b directional control 0d6h ptbdir port b output value 0d5h ptbout port b input value 0d4h ptbin port a special function 0d3h ptasfr port a directional control 0d2h ptadir port a output value 0d1h ptaout port a input value 0d0h ptain
z8e001 zilog z8plus otp microcontroller ds001101-z8x0400 p r e l i m i n a r y 31 note: the preceding result does not necessarily reflect the ac- tual output value. if an external error is holding an output pin either high or low against the output driver, the soft- ware read returns the required value, not the actual state caused by the contention. when a bit is defined as an out- put, the schmitt-trigger on the input is disabled to save power. updates to the output register takes effect based upon the timing of the internal instruction pipeline, but is referenced to the rising edge of the clock. the output register can be read at any time, and returns the current output value that is held. no restrictions are placed on the timing of reads and/or writes to any of the port registers with respect to the others; however, care should be taken when updating the directional control and special function registers. when updating a directional control register, the special function register should first be disabled. if this precaution is not taken, spurious events could take place as a result of the change in port i/o status. this precaution is especially important when defining changes in port b, as the spurious event referred to above could be one or more interrupts. clearing of the sfr register should be the first step in con- figuring the port, while setting the sfr register should be the final step in the port configuration process. to ensure deterministic behavior, the sfr register should not be writ- ten until the pins are being driven appropriately, and all ini- tialization has been completed. port a port a is a general-purpose port. figure 26 features a block diagram of port a. each of its lines can be independently programmed as input or output via the port a directional control register (ptadir at 0d2h) as seen in figure 27. a bit set to a 1 in ptadir configures the corresponding bit in port a as an output, while a bit cleared to 0 configures the corresponding bit in port a as an input. the input buffers are schmitt-triggered. bits programmed as outputs can be individually programmed as either push- pull or open drain by setting the corresponding bit in the special function register (ptasfr, figure 27). figure 26. port a directional control register d7 d6 d5 d4 d3 d2 d1 d0 0 = input 1 = output ptadir register register 0d2h figure 27. port a configuration with open-drain capability and schmitt-trigger pin pa0epa7 ptain.bitn n = 0...7 ptaout.bitn n = 0...7 ptasfr.bitn n = 0...7 ptadir.bitn n = 0...7
z8e001 z8plus otp microcontroller zilog 32 p r e l i m i n a r y ds001101-z8x0400 port a register diagrams figure 28. port a input value register figure 29. port a output value register d7 d6 d5 d4 d3 d2 d1 d0 register 0d0h ptain port a bit n current input value (only updated for pins in input mode) d7 d6 d5 d4 d3 d2 d1 d0 register 0d1h ptaout port a bit n current output value
z8e001 zilog z8plus otp microcontroller ds001101-z8x0400 p r e l i m i n a r y 33 figure 30. port a directional control register figure 31. port a special function register d7 d6 d5 d4 d3 d2 d1 d0 register 0d2h ptadir 1 = bit n set as an output 0 = bit n set as an input d7 d6 d5 d4 d3 d2 d1 d0 register 0d3h ptasfr 1 = bit n in open-drain mode 0 = bit n in push-pull mode
z8e001 z8plus otp microcontroller zilog 34 p r e l i m i n a r y ds001101-z8x0400 port b port b description port b is a 5-bit (bidirectional), cmos-compatible i/o port. these five i/o lines can be configured under software con- trol to be an input or output, independently. input buffers are schmitt-triggered. see figure 33 through figure 36 for diagrams of all five port b pins. in addition to standard input/output capability on all five pins of port b, each pin provides special functionality as shown in the following table: special functionality is invoked via the port b special func- tion register. see figure 32 for the arrangement and control conventions of this register. table 8. port b special functions port pin input special function output special function pb0 stop mode recovery input none pb1 none timer0 output pb2 irq3 none pb3 comparator reference input none pb4 comparator signal input/irq1/irq4 none figure 32. port b special function register d7 d6 d5 d4 d3 d2 d1 d0 register 0d7h ptbsfr 1 = enable pb0 as smr input 0 = no special functionality 1 = enable pb1 as timer0 output 0 = no special functionality 1 = enable pb2 as irq3 input 0 = no special functionality reserved (must be 0) 1 = analog comparator on pb3 & pb4 0 = digital inputs on pb3 & pb4 1 = pb4 interrupts enabled 0 = pb4 interrupts disabled
z8e001 zilog z8plus otp microcontroller ds001101-z8x0400 p r e l i m i n a r y 35 port b?pin 0 configuration figure 33. port b pin 0 diagram pin pb0 ptbout.bit0 ptbsfr.bit0 ptbdir.bit0 ptbdir.bit0 ptbin.bit0 smr smr flag reset
z8e001 z8plus otp microcontroller zilog 36 p r e l i m i n a r y ds001101-z8x0400 port b?pin 1 configuration figure 34. port b pin 1 diagram pin pb1 timer0 ptbout.bit1 ptbsfr.bit1 ptbdir.bit1 ptbdir.bit1 ptbin.bit1 output m u x
z8e001 zilog z8plus otp microcontroller ds001101-z8x0400 p r e l i m i n a r y 37 port b?pin 2 configuration figure 35. port b pin 2 diagram pin pb2 ptbout.bit2 ptbsfr.bit2 ptbdir.bit2 ptbdir.bit2 ptbin.bit2 edge detect logic irq3
z8e001 z8plus otp microcontroller zilog 38 p r e l i m i n a r y ds001101-z8x0400 port b?pins 3 and 4 configuration figure 36. port b pins 3 and 4 diagram pin pb3 ptbout.bit3 ptbsfr.bit3 ptbdir.bit3 ptbdir.bit4 ptbin.bit4 edge detect logic irq1 irq4 + an in ref ptbdir.bit3 ptbin.bit3 pin pb4 ptbout.bit4 ptbdir.bit4 ptbsfr.bit4 m u x -
z8e001 zilog z8plus otp microcontroller ds001101-z8x0400 p r e l i m i n a r y 39 port b control registers figure 37. port b input value register figure 38. port b output value register figure 39. port b directional control register d7 d6 d5 d4 d3 d2 d1 d0 register 0d4h ptbin port b bit n current input value reserved (must be 0) (only updated for pins in input mode) d7 d6 d5 d4 d3 d2 d1 d0 register 0d5h ptbout port b bit n current output value reserved (must be 0) d7 d6 d5 d4 d3 d2 d1 d0 register 0d6h ptbdir reserved (must be 0) 1 = bit n set as output 0 = bit n set as input
z8e001 z8plus otp microcontroller zilog 40 p r e l i m i n a r y ds001101-z8x0400 port b control registers (continued) figure 40. port b special function register d7 d6 d5 d4 d3 d2 d1 d0 register 0d7h ptbsfr 1 = enable pb0 as smr input 0 = no special functionality 1 = enable pb1 as timer0 output 0 = no special functionality 1 = enable pb2 as irq3 input 0 = no special functionality reserved (must be 0) 1 = analog comparator on pb3 & pb4 0 = digital inputs on pb3 & pb4 1 = pb4 interrupts enabled 0 = pb4 interrupts disabled
z8e001 zilog z8plus otp microcontroller ds001101-z8x0400 p r e l i m i n a r y 41 i/o port reset conditions full reset port a and port b output value registers are not affected by reset . on reset , the port a and port b directional control reg- isters is cleared to all zeros, which defines all pins in both ports as inputs. on reset , the directional control registers redefine all pins as inputs, and the port a and port b input value registers overwrites the previously held data with the current sample of the input pins. on reset , the port a and port b special function registers is cleared to all zeros, which deactivates all port special functions. note: the smr and wdt timeout events are not full device resets. the port control registers are not affected by ei- ther of these events. analog comparator the z8e001 includes one on-chip analog comparator. pin pb4 has a comparator front end. the comparator reference voltage is on pin pb3. comparator description the on-chip comparator can process an analog signal on pb4 with reference to the voltage on pb3. the analog func- tion is enabled by programming the port b special function register bits 3 and 4. when the analog comparator function is enabled, bit 4 of the input register is defined as holding the synchronized out- put of the comparator, while bit 3 retains a synchronized sample of the reference input. if the interrupts for pb4 are enabled when the comparator special function is selected, the output of the comparator generates interrupts. comparator operation the comparator output reflects the relationship between the analog input to the reference input. if the voltage on the an- alog input is higher than the voltage on the reference input, then the comparator output is at a high state. if the voltage on the analog input is lower than the voltage on the reference input, then the analog output will be at a low state. comparator definitions v icr the usable voltage range for the positive input and reference input is called the common mode voltage range (v icr ). note: the comparator is not guaranteed to work if the input is outside of the v icr range. v offset the absolute value of the voltage between the positive input and the reference input required to make the comparator output voltage switch is the input offset voltage (v offset ). i io for the cmos voltage comparator input, the input offset current (i io ) is the leakage current of the cmos input gate. halt mode the analog comparator is functional during halt mode. if the interrupts are enabled, an interrupt generated by the comparator will cause a return from halt mode. stop mode the analog comparator is disabled during stop mode. the comparator is powered down to prevent it from drawing any current.
z8e001 z8plus otp microcontroller zilog 42 p r e l i m i n a r y ds001101-z8x0400 input protection all i/o pins on the z8e001 have diode input protection. there is a diode from the i/o pad to v cc and v ss (figure 41). however, on the z8e001, the reset pin has only the input protection diode from pad to v ss (figure 42). the high-side input protection diode was removed on this pin to allow the application of high voltage during the otp programming mode. for better noise immunity in applications that are exposed to system emi, a clamping diode to v cc from this pin can be required to prevent entering the otp programming mode or to prevent high voltage from damaging this pin. figure 41. i/o pin diode input protection pin v cc v ss figure 42. reset pin input protection pin v ss reset
z8e001 zilog z8plus otp microcontroller ds001101-z8x0400 p r e l i m i n a r y 43 package information figure 43. 18-pin dip package diagram figure 44. 18-pin soic package diagram
z8e001 z8plus otp microcontroller zilog 44 p r e l i m i n a r y ds001101-z8x0400 package information (continued) figure 45. 20-pin ssop package diagram
z8e001 zilog z8plus otp microcontroller ds001101-z8x0400 p r e l i m i n a r y 45 ordering information for fast results, contact your local zilog sales office for assistance in ordering the part(s) required. standard temperature 18-pin dip Z8E00110SSC 18-pin soic z8e00110hsc 20-pin ssop z8e00110psc extended temperature 18-pin dip z8e00110pec 18-pin soic z8e00110sec 20-pin ssop z8e00110hec codes preferred package p = plastic dip longer lead time s = soic h = ssop preferred temperature s = 0?c to +70?c e = e40?c to +105?c speed 10 = 10 mhz environmental c = plastic standard example: z 8e001 10 p s c is a z86e001, 10 mhz, dip, 0? to +70?c, plastic standard flow environmental flow temperature package speed product number zilog prefix
z8e001 z8plus otp microcontroller zilog 46 p r e l i m i n a r y ds001101-z8x0400 pre-characterization product: the product represented by this document is newly introduced and zilog has not completed the full characterization of the product. the document states what zilog knows about this product at this time, but additional features or non-conformance with some aspects of the document may be found, either by zilog or its customers in the course of further application and characterization work. in addition, zilog cautions that delivery may be uncertain at times, due to start-up yield issues. development projects: customer is cautioned that while reasonable efforts will be employed to meet performance objectives and milestone dates, development is subject to unanticipated problems and delays. no production release is authorized or committed until the customer and zilog have agreed upon a product specification for this project. low margin: customer is advised that this product does not meet zilog's internal guardbanded test policies for the specification requested and is supplied on an exception basis. customer is cautioned that delivery may be uncertain and that, in addition to all other limitations on zilog liability stated on the front and back of the acknowledgement, zilog makes no claim as to quality and reliability under the document. the product remains subject to standard warranty for replacement due to defects in materials and workmanship. ?1999 by zilog, inc. all rights reserved. information in this publication concerning the devices, applications, or technology described is intended to suggest possible uses and may be superseded. zilog, inc. does not assume liability for or provide a representation of accuracy of the information, devices, or technology described in this document. zilog also does not assume liability for intellectual property infringement related in any manner to use of information, devices, or technology described herein or otherwise. except with the express written approval of zilog, use of information, devices, or technology as critical components of life support systems is not authorized. no licenses are conveyed, implicitly or otherwise, by this document under any intellectual property rights. zilog, inc. 910 east hamilton avenue, suite 110 campbell, ca 95008 telephone (408) 558-8500 fax 408 558-8300 internet: http://www.zilog.com

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